KAIST researchers boost 2D semiconductor performance 260-fold without structural damage

Researchers have developed a new doping process technology capable of boosting the low-voltage performance of two-dimensional semiconductors by up to 260 times without damaging their atomic layers.

The National Research Foundation of Korea announced Monday that a joint research team led by Professors Choi Sung-yool, Kim Yong-hun and Kang Ki-bum at KAIST had developed a technique that uses an ultrathin double protective layer to shield molybdenum disulfide (MoS2) 2D semiconductors while enabling selective, high-concentration electron doping in targeted areas.

Two-dimensional semiconductors, which are only a single atomic layer thick, have drawn attention as a next-generation material for ultra-miniaturized chips. However, conventional doping methods used in silicon semiconductor manufacturing — such as ion implantation and thermal diffusion — are difficult to apply selectively to specific regions of 2D materials.

Commercializing 2D semiconductors requires innovative process technology that can preserve their delicate atomic structure while doping only the desired areas.

The research team addressed this challenge by developing a double protective layer composed of two types of ultrathin films, each just 2 nanometers thick.

The protective layer acts as a "chemical filter," deflecting the strong physical impact of plasma while allowing only the reactive species needed for doping — NHx active radicals — to pass through. As a result, the semiconductor's crystal structure is kept intact while electron concentration rises sharply, reducing contact resistance to one thirty-second of its original level.

The team also achieved what it calls "area-selective resistance control" — pinpointing and doping only the specific locations along the electron pathway where resistance poses a problem, much like using tweezers to target a precise spot. This pushed current flow at very low voltages up by as much as 260 times.

The technology stands out for its ability to preserve the crystallinity of 2D semiconductors while selectively lowering resistance only in targeted regions. Researchers expect it to find applications in ultra-miniaturized low-power logic devices, monolithic 3D semiconductors and 2D CMOS circuits.

However, the researchers noted that additional verification is needed before the technique can be applied in semiconductor manufacturing — including confirmation of doping uniformity, reduction of process time, and precise control of doped regions in extremely miniaturized devices.

"Our goal is to combine this with complementary p-type 2D semiconductor technology and verify its performance and low-power effects in actual 2D CMOS circuits and monolithic 3D integrated semiconductors," said Professor Choi Sung-yool.

The research was supported by the Ministry of Science and ICT and the National Research Foundation of Korea through their nano and materials technology development project and mid-career researcher support project. The findings were published in the international journal Advanced Materials on Aug. 1.