KAIST cracks electrical bottleneck in ultrathin semiconductors

Researchers have developed a new technology that can efficiently supply electricity to ultrathin semiconductors just a few atoms thick — a potential breakthrough for building smaller, denser next-generation low-power AI chips.

KAIST announced Wednesday that a research team led by Professor Seo Jun-ki of the Department of Chemical and Biomolecular Engineering developed a "universal van der Waals tunneling injector" using tin diselenide (SnSe₂), in collaboration with researchers from Yonsei University, the Beijing Computational Science Research Center in China, the Korea Institute of Science and Technology, Ulsan National Institute of Science and Technology (UNIST), and Samsung Electronics.

Transistors are microscopic switches that control the flow of electricity. They come in two types: n-type, in which electrons carry the current, and p-type, in which positively charged "holes" — spaces left by missing electrons — do the work. Real semiconductor chips widely use a structure called CMOS, or complementary metal-oxide-semiconductor, which combines both types.

Two-dimensional semiconductors, which are only a few atoms thick, have drawn growing attention as a way to overcome the physical limits of miniaturization. Their extreme thinness allows them to be stacked in multiple layers, enabling more transistors to be packed into the same surface area.

Supplying electricity smoothly to these ultrathin semiconductors, however, has been a persistent challenge. Direct contact with conventional metal electrodes can damage the semiconductor or create barriers that impede the movement of electrons and holes. Compounding the problem, n-type and p-type semiconductors require different conditions for charge injection, meaning separate electrodes had to be used for each.

The research team solved this problem with a single material: tin diselenide. Rather than forming strong chemical bonds with other semiconductors, tin diselenide binds through weak "van der Waals forces" between atoms, minimizing damage to the ultrathin semiconductor while creating a smooth contact interface.

The material also spontaneously forms favorable pathways for electrons or holes depending on the type of semiconductor it is connected to.

In a p-type WSe₂ transistor using tin diselenide, the maximum drive current increased more than 1,000 times compared with a device using conventional nickel electrodes. An n-type MoS₂ transistor also achieved an on/off current ratio — a measure of how effectively a transistor switches between conducting and non-conducting states — exceeding 1 billion.

The team also fabricated a CMOS inverter by combining the two transistors and confirmed that it operated stably under repeated electrical signals.

If large-area manufacturing and integration processes are added to the technology, researchers expect it could enable three-dimensional semiconductors in which multiple layers of atom-thick two-dimensional materials are stacked. That, in turn, could lead to next-generation AI semiconductors that pack more transistors into the same area, boosting performance while cutting power consumption.

"This work demonstrates that the most demanding gateway for charge to enter and exit a monolayer two-dimensional semiconductor can be addressed with a single type of material," Professor Seo said. "When combined with direct-growth and large-area process technology, it could accelerate the practical realization of low-power two-dimensional CMOS integrated circuits."

He added that the goal of follow-up research is to develop a low-power, high-density three-dimensional logic platform that combines the advantages of monolayer semiconductors with the maturity of existing silicon process technology.

The findings were published in the international journal Advanced Materials.