KAIST researchers crack key 3D memory challenge, boosting AI chip performance

South Korean researchers have developed a technology to improve the performance and stability of next-generation three-dimensional memory chips, with potential applications in high-density, low-power AI semiconductors.

KAIST announced Thursday that a research team led by Kwon Ji-min, a professor in the School of Electrical Engineering, has developed a new multilayer interlayer dielectric structure that reduces defects in oxide vertical channel transistors (VCTs). The team worked jointly with researchers from UNIST, Yonsei University, the Korea Research Institute of Chemical Technology, Seoul National University of Science and Technology and Seoul National University.

As semiconductor miniaturization approaches its physical limits, three-dimensional architectures — which stack components vertically to increase density — have drawn growing attention. Vertical channel transistors allow more devices to be packed into a limited area by orienting the current-carrying channel vertically.

Using oxide semiconductors as the channel material is particularly advantageous for low-power memory because it reduces leakage current. However, a persistent problem has been the formation of "oxygen vacancies" — gaps left when oxygen atoms escape from within the oxide semiconductor — which alter electrical properties and degrade device stability.

Replenishing that oxygen is not straightforward, either. If oxygen migrates all the way to the metal electrode, it oxidizes the electrode and can actually worsen device performance.

To address this, the team developed a multilayer interlayer dielectric composed of silicon nitride, silicon dioxide and silicon nitride. The structure acts as a kind of "oxygen tunnel," directing oxygen toward the oxide semiconductor where it is needed while blocking its migration toward the electrode.

This approach simultaneously fills oxygen vacancies within the oxide semiconductor and suppresses unwanted oxidation of the electrode. In testing, the team applied the oxygen tunnel to an indium tin oxide (ITO) vertical channel transistor, achieving a current density of 436 μA/μm while improving both performance and reliability.

The technology also demonstrated strong durability. After more than 10 million operating stress cycles, the threshold voltage shift remained below 50 mV.

The team also evaluated system-level performance by combining conventional silicon-based CMOS with oxide semiconductors. The results confirmed the potential to shrink memory cell area, extend data retention time and enhance compute-in-memory (CIM) performance.

Compute-in-memory performs calculations directly within the memory unit where data is stored. Because it eliminates the need to repeatedly transfer large volumes of data between memory and a processor — as conventional computers do — it can reduce the power consumption and processing delays that arise during AI computation.

"Just as building a tall skyscraper requires making it structurally sound, not just adding more floors, the key to 3D semiconductors is ensuring stable operation as more layers are stacked," Kwon said. "We expect this technology to accelerate the development of next-generation memory semiconductors that increase AI processing speed while reducing power consumption."

The findings were published in the international journal Advanced Functional Materials.