Samsung achieves world first in reducing AI chip wiring resistance

Samsung Electronics has become the first company in the world to demonstrate a technology capable of solving the problem of rising wiring resistance as semiconductor circuits shrink — a foundational advance for improving the performance and power efficiency of AI and high-performance computing chips.

Samsung Advanced Institute of Technology, the company's central research arm known as SAIT, announced Friday that it had developed a technique using trace amounts of carbon to control the grain size and orientation of ruthenium — a next-generation wiring material — dramatically lowering resistance in ultrafine metal interconnects.

The findings were published in the journal Science on Aug. 13 (local time). The paper lists 13 researchers in total, 11 of whom are affiliated with Samsung's SAIT, with additional contributors from the Gwangju Institute of Science and Technology and the Massachusetts Institute of Technology.

As competition over AI chip performance has intensified, the ability to pack circuits ever more tightly has become increasingly critical. The challenge is that as chips shrink, the metal wires connecting transistors also narrow, making it harder for electricity to flow.

Once wiring falls below a certain width, resistance rises sharply. Electrons traveling through the metal collide frequently with grain boundaries — the interfaces between individual metal crystals — impeding their movement.

Higher wiring resistance slows signal transmission inside a chip and increases power consumption and heat generation. Even when transistor performance improves, signal delays in the interconnects can cap overall chip performance.

The SAIT team addressed this by introducing a trace carbon-based promoter into ruthenium, which has drawn attention as a next-generation wiring material. The carbon causes the small crystals that make up ruthenium to align uniformly in a single direction.

Using this approach, the researchers produced a thin film in which more than 99 percent of ruthenium crystals are oriented in the same direction. The alignment reduces the obstacles electrons encounter as they move, allowing current to flow more smoothly.

Critically, the team achieved high-level crystal alignment even on amorphous insulating films of the kind used in actual semiconductor manufacturing. When the technology was applied to nanometer-scale wiring, line resistance fell by about 45 percent compared with conventional ruthenium interconnects made without the carbon promoter.

The technology is expected to help boost the performance of AI accelerators and HPC chips. As the volume of computation AI chips must handle grows, techniques that raise performance while cutting power consumption are becoming ever more important.

As circuits continue to shrink, resistance and signal delay in the metal interconnects — not just in the transistors themselves — increasingly determine overall chip performance.

Samsung Electronics said the technology "presents a new approach that can fundamentally alleviate the problem of rising resistance in ultrafine wiring," adding that if commercialized, it "is expected to contribute to faster electrical signal transmission and reduced power loss inside advanced logic semiconductors for AI and HPC applications, improving both chip performance and power efficiency."