Samsung Electronics unveils 'CUBE' strategy to push past memory technology limits

Samsung Electronics has laid out a vision to strengthen its technology leadership through higher memory capacity and improved power efficiency.

Choi Jang-seok, head of product planning at Samsung Electronics' Device Solutions division Memory Business, delivered the keynote address at the Memory Executive Summit of Semicon Taiwan 2026, an international semiconductor exhibition held Tuesday (local time) in Taipei, Taiwan, where he unveiled the company's CUBE strategy for overcoming memory technology limits.

The CUBE strategy outlines Samsung's technology improvement vision across five elements: Capacity, Utilization, Bandwidth and Efficiency — covering power and thermal performance.

"We will no longer be constrained by PCB area," Choi said at the event. "We will scale vertically to increase memory capacity without expanding board area."

He added that 3D architecture is not simply about stacking layers. "The key is how each layer is utilized," he said. "Samsung is optimizing the logic and memory layout to eliminate data processing latency."

On bandwidth, Choi said the company can achieve dramatic improvements "by significantly reducing the distance between dies to form a vertical highway."

He also said "the ultimate goal of 3D is to reduce the energy required to move a single bit of data," adding that "Samsung is maximizing performance per watt by improving structural efficiency."

Samsung Electronics is currently developing HBM5, its eighth-generation high bandwidth memory chip, targeting twice the performance of the previous-generation HBM4E, a 20 percent improvement in performance per watt, and a 20 percent reduction in thermal resistance.

The company's next-generation 3D memory architecture, zHBM — the first of its kind unveiled in the industry — targets performance eight times that of HBM4E, a threefold improvement in performance per watt, and a 75 to 90 percent reduction in thermal resistance.

Also on the roadmap is zNAND-O, a next-generation high-performance NAND flash chip scheduled for sample availability in 2028. It offers bit density 10 times higher than DRAM to support the large-scale capacity demands of large language models, and its strengths include read bandwidth and power efficiency seven times greater than conventional NAND.

Samsung Electronics is rapidly expanding its market leadership by combining this technology edge with the industry's largest production capacity. Market research firm Omdia projects the company's DRAM output this year at approximately 8.175 million 300-millimeter wafers annually — well ahead of SK hynix at roughly 6.66 million wafers and Micron at roughly 3.6 million.

Samsung's NAND wafer output this year is also projected at approximately 4.77 million wafers, expected to far outpace SK hynix and Solidigm at roughly 2.79 million combined.