Samsung Electronics unveils next-gen 3D memory 'zHBM,' stacking chips atop GPUs

Samsung Electronics has pulled back the curtain on a new lineup of memory chips aimed at powering the AI era, unveiling next-generation 3D memory products as it looks to meet demand that conventional high-bandwidth memory alone can no longer satisfy.

At FMS 2026, which opened Tuesday (local time) at the Santa Clara Convention Center in California, Samsung became the first in the industry to publicly display prototypes of zHBM and z-NAND-O — technologies the company is positioning as successors to HBM.

Executive Vice President Lee Jin-yeop of the Flash Development Division and Senior Vice President Kim Gyeong-ryun of the DRAM Development Division delivered keynote addresses that day, highlighting Samsung's technology for maximizing the performance and power efficiency of AI systems through zHBM and z-NAND-O.

Samsung presented zHBM as an alternative to conventional HBM. Where today's systems place HBM alongside a GPU, zHBM stacks HBM vertically on top of the GPU itself, shortening the distance data must travel between the processor and memory. That shorter path supports the ultra-fast data processing required for training and inference in large-scale AI models.

"A next-generation interface system incorporating zHBM delivers up to eight times higher performance than HBM5," Kim said. "It improves power efficiency by up to three times compared with HBM5 and cuts thermal resistance by more than half, maximizing the stability and power efficiency of high-capacity, high-bandwidth systems."

zHBM also supports customer-specific design. By inserting tailored IP blocks — circuit-level design units that implement specific functions — between the memory and GPU, customers can expand memory capacity and enhance accelerator performance to suit their needs.

z-NAND-O is a next-generation, high-performance NAND flash chip Samsung is developing. It combines the vertical stacking technology of conventional V-NAND with through-silicon via technology to package four or eight semiconductor chips in a 3D configuration.

Optimized for on-device AI environments, the product offers high space efficiency, wide data-loading bandwidth and fast response times, enabling high performance in settings that demand real-time processing of large-scale data.

Samsung also used the keynote to unveil what it called an industry first: the 10th-generation V-NAND "V10 BV-NAND," with more than 400 layers. The chip applies wafer-bonding technology — which fuses two or more wafers vertically — and a three-stack architecture that divides cells into three stacks manufactured separately before stacking them vertically, boosting both performance and power efficiency.

Memory density is about 58 percent higher than in the ninth-generation product, allowing more data to be stored in the same footprint. Read and write performance and I/O speed also improve on the previous generation, giving Samsung a competitive edge in the high-performance, high-capacity NAND market.

Samsung plans to use FMS 2026, which runs through Thursday, to emphasize its memory and storage technology capabilities for next-generation AI infrastructure.

In addition, the company said it will leverage its strengths as an integrated device manufacturer spanning memory chips, foundry and advanced packaging to shorten the time from product design to mass production, with a focus on delivering customized AI semiconductors for customers.